The present invention relates to a memory module composed of a plurality of semiconductor memory devices and, in particular, to a memory module having parity and capable of performing a read-modify-write (RMW) operation.
A technique for composing a memory module having parity, and providing external pins for controlling high-speed access of input and output data is disclosed in "DRAM Module Data Book", Vol. 1992/93, p 165, published by Samsung Electronics Co. Ltd.
FIG. 1 illustrates the construction of a prior art memory module, according to that disclosed in the above data book e.g., a 4Mx9 memory module 1 (wherein "x9" indicates the number (9) of bits constituting one word, the word being composed of 8 data bits and one parity bit, and "4M indicates the capacity (4 Meg) of the module). As shown in FIG. 1, the memory module 1 includes two 4Mx4 semiconductor memory devices 3 and 5 and a single 4Mx1 semiconductor memory device 7. The 4Mx4 semiconductor memory devices 3 and 5 each have common data input and output pins DQ1.about.DQ4 and the 4Mx1 semiconductor memory device 7 has a separate data input pin DIN and output pin DOUT. Data input and output pins DQ1.about.DQ4 of memory device 3 are coupled to data input and output pins DQM1.about.DQM4 of memory module 1 whereas data input and output pins DQ1.about.DQ4 of memory device 5 are coupled to data input and output pins DQM5.about.DQM9 of memory module 1. Further, data input pin DIN and data output pin DOUT of memory device 7 are joined together to data input and output pin DQM9 for processing the parity data of memory module 1. Meanwhile, the output enable signal pins OE of both 4Mx4 semiconductor memory devices 3 and 5 (supplying output enable signals to each device) are coupled to a ground potential Vss. Furthermore, each memory device 3, 5 and 7 contains pins to which address signals and control signals are applied (for example, row address strobe signal RAS, column address strobe signal CAS, write enable signal WE, and so on). However, detailed descriptions of these signals are unnecessary and will be omitted.
In a memory module such as that of FIG. 1, the method of data input and output in a x4 semiconductor memory device is different from that of a x1 semiconductor memory device. Accordingly, the output enable signal pins OE of the 4Mx4 semiconductor memory devices 3 and 5 are coupled to ground potential Vss while data input pin DIN and data output pin DOUT of the 4Mx1 semiconductor memory device 7 are joined together in a unitary format. That is, each bit line of the x4 semiconductor memory device has a common data pin for both data input and output and each x4 device has a single data output enable signal pin for controlling the data input and output. In contrast, the x1 semiconductor memory device has a pin for both data input DIN and output DOUT, and no output enable signal pin.
Since the number of data lines typically required to interface the memory module with a CPU, for example, is nine (for an eight-bit word having one parity bit), the data input and output pins of the x1 semiconductor memory device in FIG. 1 must be commonly connected to pin DQM9. This is not a problem in most applications, such as when the CPU performs a standard read or write cycle. In such cases, the CPU prevents read operations from the memory module by driving its data output lines to a high-impedance state. Conversely, when output enable signal OE of the 4Mx4 semiconductor memory devices, is "low", the CPU reads or writes data from/to the memory module 1 according to timing controlled by row address strobe signal RAS, column address strobe signal CAS and write enable signal WE. However, due to the constraints of the design of a memory module such as that in FIG. 1, problems arise when the CPU selects a read-modify-write operation, as will be discussed below.
A technique for performing a read-modify-write operation during a single operation cycle of a memory module is well-known in the present field. In this technique, the write enable signal WE is dispensably activated, at least after as much time has passed as that needed for accessing the column address strobe signal CAS. However, because it provides no way to selectively control input and output, the x1 semiconductor memory device of FIG. 1 cannot discriminate the read-modify-write cycle selected by the CPU from a general read and write cycle. More particularly, although the read-modify-write operation of 4Mx4 semiconductor memory devices 3 and 5 can be reliably controlled by the output enable signal provided to each pin OE, in the 4Mx1 semiconductor memory device 7, a data conflict between the input data line and the output data line is created because they are joined to each other in the unitary format. Consequently, the parity bit of the conventional memory module of FIG. 1 is unable to perform the read-modify-write operation selected by the CPU.